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Ordering number : ENN6124
CMOS IC
LC73815M
FSK 1200 Baud Modem and DTMF Receiver
Overview
The LC73815M is a telephone IC that integrates on a single chip both an FSK modem, which receives pre-call reporting services such as caller ID and performs other data send/receive functions, and a DTMF receiver circuit that can handle remote control functions for telephone answering machine applications.
* Digital guard timer circuits for the DTMF signal detection signal pins * Operating voltage range: 4.5 to 5.5 V * Low-power mode that can contribute to energy savings * 36-pin package (MFP-36S)
Package Dimensions
unit: mm 3129-MFP36S
[LC73815M]
36 19
Applications
Pre-call reporting services, such as Caller ID, reception, other data send/receive functions, and remote control of telephone answering machine applications.
Features
* FSK modem (1200 bps) * Circuit that automatically generates the start and stop bits used during FSK modulation * Circuit that automatically generates the continuous mark signal at the start of transmission in FSK modulation mode * Circuit that automatically inserts the idle bits (5 or more bits) used in FSK modulation mode * Built-in clock synchronous I/O shift register * Detection of all 16 DTMF signals
9.2 10.5 0.65 0.25 2.25 2.5max 0.4 0.8 0.85 7.9
1
15.3
18
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Maximum input current Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max IIN max Pd max Topr Tstg Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -10 to +10 250 -30 to +70 -40 to +125 Unit V V mA mW C C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D2200RM (OT) No. 6124-1/17
0.1
SANYO: MFP36S
LC73815M Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V
Parameter Supply voltage Symbol VDD IDD(OP1) VDD = 5.0 V, when the DTMF receiver is used. Operating current drain IDD(OP2) VDD = 5.0 V, during FSK reception IDD(OP3) VDD = 5.0 V, during FSK transmission Quiescent current Oscillator frequency IDD(ST) fOSC RES pin = low 3.5757965 3.579545 Conditions Ratings min 4.5 typ 5.0 5.5 7.5 7.5 max 5.5 10 15 15 10 3.583125 Unit V mA mA mA A MHz
DC Electrical Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V
Parameter Symbol VIH VIHS VIL VILS VIH IIL IOH IOL Conditions Pins other than ACK and RES The ACK and RES input pins Pins other than ACK and RES The ACK and RES input pins VIN = VDD VIN = GND VOUT = VDD - 0.4 V VOUT = 0.4 V 1.0 -10 -0.8 2.5 -0.4 Ratings min 0.7 VDD 0.8 VDD 0.3 VDD 0.2 VDD 10 typ max Unit V V V V A A mA mA
High-level input voltage
Low-level input voltage
Input leakage current High-level output current Low-level output current
AC Electrical Characteristics 1 (FSK reception/transmission) at Ta = 25C, VDD = 5 V, VSS = 0 V, fOSC = 3.579545 MHz
Parameter Input signal detection level Reception data transmission speed Reception frequency fACK Shift register data shift speed tCKL tCKH External oscillator input EXTOI B/V = H FSK transmission frequency FSK (Mark) 500 500 0.5 1200 2204 1300 2101 0.5 0.8 1200 tDDEM tSDATA tSDR tSCKD tSCKDR See the timing chart. See the timing chart. See the timing chart. See the timing chart. See the timing chart. 0 1.1 0 0 0.83 0.42 2.2 0.83 3.3 300 9.0 Symbol FSK reception FSK FSK (Mark) FSK (Space) Conditions Ratings min -38 1188 1180 2070 1200 1250 2150 typ max +3 1212 1320 2280 1 Unit dBm baud Hz Hz MHz ns ns Vrms Hz Hz Hz Hz Vp-p bps ms ms s ns s
(BELL202) FSK (Space) B/V = L (V.23) FSK (Mark) FSK (Space)
FSK output amplitude Transfer rate FSK modulation delay time Data output setup time DR output setup time ACK - DATA setup time ACK - DR setup time
Conditions: For the dBm ratings, 0 dBm is defined to be a 1 mW output into a 600 load.
No. 6124-2/17
LC73815M AC Electrical Characteristics 2 (DTMF reception) at Ta = 25C, VDD = 5 V, VSS = 0 V, fOSC = 3.579545 MHz
Parameter Input signal detection level Allowable twist Frequency detection band Frequency non-detection band Allowable third tone Allowable dial tone Allowable noise Input signal invalid time Input signal valid time Interdigit pause invalid time Interdigit pause valid time Guard time Input signal detection time Conditions (Present) (Absent) (Present) (Absent) tREC tREC tDO tID tGDP tGDA tDP tDA Symbol 1, 2, 3, 5, 6, 9 2, 3, 6, 9, 11 2, 3, 5, 9 2, 3, 5 2, 3, 4, 5, 9, 10 2, 3, 4, 5, 8, 9, 10 2, 3, 4, 5, 7, 9, 10 See the timing chart. See the timing chart. See the timing chart. See the timing chart. See the timing chart. See the timing chart. See the timing chart. See the timing chart. 3 0.5 40 30 20 20 20 45 20 1.5% 2 Hz 3.5 -16 22 -12 20 % dB dB dB ms ms ms ms ms ms ms ms Conditions Ratings min -45 10 typ max +0 Unit dBm dB
1. The 0 dBm level is defined to be a 1 mW output into a 600 load. 2. All combinations of the 16 DTMF signals. 3. A 40 ms DTMF signal period, and a 40 ms pause period 4. The nominal frequencies are used for DTMF signals. 5. The signal levels of the low group and high group signals are identical. 6. The tolerance for DTMF signal frequency is within 1.5% or 2 Hz. 7. Gaussian noise with a band of 0 to 3 kHz 8. Dial tone pair of 350 and 440 Hz 9. The error ratio is under 1 error in 10,000 operations. 10. Referenced to the frequency component with the lowest level in the DTMF signal. 11. Twist: the ratio of the high group tone level to the low group tone level
Note: This IC contains a Switched Capacitor Filter (SCF) circuit on chip. Since the internal SCF clock frequency is OSC/56 (= 63.92 kHz), a power supply related noise whose frequency is OSC/56 multiplied by some integer 3 kHz will prevent the ratings shown above from being achieved. Therefore, care must be taken for the power supply related noise.
Input Amplifier Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V, fOSC = 3.579545 MHz
Parameter Input offset voltage Input offset current Power supply rejection ratio Common-mode rejection ratio Open loop voltage gain 0 dB bandwidth Maximum output voltage Allowable load capacitance Allowable load resistance Common-mode input voltage range Symbol VIO IIO PSRR CMRR AO fT VO CL RL VCM No load RL 100 k VSS VIN VDD 1 kHz Conditions Ratings min -25 100 60 60 65 1.5 VDD - 0.5 100 50 3.0 typ max +25 Unit mV nA dB dB dB MHz Vp-p pF k Vp-p
No. 6124-3/17
LC73815M Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin IN+ IN- GS AGND NC FSKOUT AGCO FSKIN NC AGND NC TESTI B/V NC OSCIN OSCOUT NC VSS VDD NC S/R F/D NC DATA ACK I/O I Serial output of the FSK or DTMF received data in synchronization with the ACK input pin. Also used for serial input of FSK transmission data. Synchronization clock input for serial data readout and write. In DTMF receiver mode (EST), a high level indicates the presence of a valid DTMF signal. Monitor this pin (or the STD pin), and, after an appropriate wait period has passed, read out the data by applying four pulses to the ACK pin. Note that the received DTMF data is latched internally to the IC on the rising edge of this pin. In FSK reception mode (DR), this pin outputs a high level when the received data is valid, and goes low after the received data has been read out by applying pulse inputs to the ACK pin. In FSK transmission mode (DR), this pin indicates the input ready state for transmission data. A high level indicates that the IC is ready to accept the input of transmission data. In DTMF receiver mode (STD), a high level indicates the presence of a valid DTMF signal. The rise of this signal occurs later than that of the EST signal. However, this signal is not sensitive to burst waveforms. In FSK mode, this pin functions identically to pin 26. FSK demodulated signal output Reset input. Apply a low level to this pin when power is first applied and after low-power mode. At least 1 s of low-level input is required for the reset operation. This input controls DR during FSK reception. DR is invalid if this input is high in FSK reception mode. If this pin is low (note that it is pulled down internally) DR is enabled. This pin also functions to select continuous mark signal generation at the start of transmission mode in FSK transmission mode. Low: If the S/R pin is high, continuous mark signals are generated automatically. FSK data will be output following the continuous mark signals generated after the CPU inputs another FSK data to this pin. High: FSK is not output until the CPU inputs the next FSK data, even if the S/R pin is set high. IC test output pin I I FSK send/receive mode switching input. High: Send, Low: Receive. FSK modem/DTMF receiver operating mode switching input. High: FSK modem, Low DTMF receiver. I Ground Power supply. Connect a capacitor of at least 0.1 F between this pin and GND. I O Connect a 3.579545 MHz oscillator element between these pins. An external 3.579545 MHz may also be supplied. (Consult oscillator element manufacturers concerning the combination of their products with this IC.) I I IC test input. This pin must be tied low during normal operation. Transmission FSK frequency switching input (Bell 202, V.23) High: Bell 202, Low: V.23 I IC internal analog ground input O O I FSK signal output. This is an npn transistor emitter-follower output. Connect to pin 8 through a capacitor. Make no other connections to this pin. Connect to pin 7 through a capacitor. Make no other connections to this pin. I/O I I O O Differential operational amplifier noninverting input Differential operational amplifier inverting input Differential operational amplifier output IC internal analog ground output Function
26
EST/DR
O
27 28 29
STD/DR RDO RES
O O I
30
DRCNT
I
31 32, 33 34 35, 36
TEST01 NC TEST02 NC
O
O
IC test output pin
No. 6124-4/17
Block Diagram
VDD
VSS
RES Test output circuit
Bias circuit
TESTO1 TESTO2
AGNDI
Vref circuit
AGNDO High group bandpass filter Signal discrimination circuit Dial tone filter Low group bandpass filter Low-frequency group detection circuit FSK data determination circuit FSK demodulator circuit High-frequency group detection circuit Output signal control circuit STD/DR
IN+
IN-
AGC
Anti-aliasing filter
Code comparator circuit
GS
EST/DR ACK DATA F/D S/R RDO
LC73815M
AGCOUT
I/O control circuit
FSKIN
TESTI FSK modulator circuit
Test input circuit
FSKOUT DRCNT
Timing generator
OSCIN
OSCOUT
B/V
A12311
No. 6124-5/17
LC73815M Timing Chart (DTMF mode) Timing chart for the normal state (when DTMF signal #n and #n+1 have been input.)
INPUT tDP #n tDA #n+1
EST tGDP STD tGDA
ACK >20 s DATA LSB #n MSB LSB #n+1 MSB
A12312
When a DTMF signal (#n) is separated into two events due to a burst waveform or other problem.
tDO
INPUT
#n
#n
#n+1
EST
STD
ACK
DATA LSB
#n MSB LSB
#n MSB LSB
#n+1 MSB
A12313
No. 6124-6/17
LC73815M When a pseudo-DTMF signal consisting of noise (#n + ) is input.
tREC
INPUT tREC
#n #n+
#n+1
EST
STD
ACK
DATA
#n
#n+
#n+1
A12314
When the output data is incorrect due to displacement of the input clock
tID INPUT #n #n+1 #n+2
EST
STD
ACK
DATA LSB
#n MSB LSB
#n+2 MSB
A12315
Note: The output data is output from the DATA pin in response to four pulses applied as a set to the ACK pin. The output data are composed of four ACK pulses.There must be a wait time of at least 20 s between the last of these 4 ACK pulses and the next ACK pulse.
No. 6124-7/17
LC73815M Timing Chart (FSK mode reception)
Parity RDO b7 P Start 1 Stop 0 b1 b2 b3 b4 b5 b6 b7 P 1 0 b1 b2 b3 b4 b5 b6 b7 p 1
DR
ACK
DATA
b1
b2 b3 b4 b5 b6 b7
P
b1
b2 b3 b4 b5 b6 b7
P
RDO
P
STOP
START
b1
b2
tSDATA
RDO
tSDR
DATA b1 b2
tCKL
tCKH
ACK fACK
DR
DATA
b5 tSCKD
b6
b7
P
tSCKDR ACK
A12316
No. 6124-8/17
LC73815M
FSK
STOP START b1n
b2n
b3n
b4n
b5n
b6n
b7n
Pn
STOP START b1n+1 b2n+1 b3n+1 b3n+1 b4n+1 b5n+1
TDDEM
RDO
STOP START b1n
b2n
b3n
b4n
b5n
b6n
b7n
Pn
STOP START b1n+1 b2n+1 b3n+1 b3n+1 b4n+1
DR
ACK
DATA
b1n-1
b2n-1 b3n-1 b4n-1 b5n-1 b6n-1 b7n-1
Pn-1
b1n
b2n
b3n
b4n
b5n
b6n
A12317
Channel seizure signal FSK 01010101010101010101
mark signal 1111111111111111111 Message data
RESET
OSCO
RDO
0101010101010101--Invalid data
1111111111111111---
Message data
invalid data
DR
ACK
A12318
No. 6124-9/17
LC73815M Timing Chart (FSK mode transmission)
DRCNT
S/R
ACK
DATA D0 to D7
DR Start bit FSK Idling D0 Start bit
A12319
D1
D2
D3
D4
D5
D6
D7
Idling
DRCNT
S/R
ACK
DATA
#1
#2
#3
#4
DR Idling FSK Start bit #1 Start bit #2 Start bit #3 Start bit Idling #4
A12320
Stop bit
Stop bit
Stop bit
Idling
Stop bit
At least 5 bits of idling inserted
No. 6124-10/17
LC73815M
DRCNT
S/R
ACK
DATA D0 to D7
DR Start bit DC bias FSK D0 D1 D2 D3 D4 D5 Start bit D6 D7
Idling
A12321
DRCNT
S/R
ACK
DATA
#1
#2
#3
#4
DR DC bias FSK Start bit #1 Start bit #2 Start bit #3 Start bit Idling #4
A12322
Stop bit
Stop bit
Stop bit Idling
Stop bit
At least 5 bits of idling inserted
No. 6124-11/17
LC73815M
DRCNT
S/R
ACK
DATA
#1
#2
DR Idling FSK DC bias Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Idling Start bit D0 D1 D2 D3 D4 D5 D6 D7 Idling #1 At least 5 bits of idling inserted
A12323
Stop bit
#2
DRCNT
S/R
ACK
DATA
#1
#2
DR Idling FSK DC bias #1 At least 5 bits of idling inserted
A12324
Idling
DC bias
Start bit D0 D1 D2 D3 D4 D5 D6 D7
Stop bit Idling
Start bit D0 D1 D2 D3 D4 D5 D6 D7
Stop bit
Idling #2
No. 6124-12/17
LC73815M Pin Internal Connection
Pin No. Pin Internal connection
VDD IN- 1 VDD
1 2 3 IN+ IN- GS
- +
IN+ 2
VDD
GS 3
A12325
VDD
VDD
AGNDI 4
4 10 AGNDI AGNDO
VDD
AGNDO 10
VDD VDD
6 FSKOUT
FSKOUT 6
VDD +
VDD
7 8 AGCO FSKIN
FSKIN 8
- +
1/2VDD TESTI 12
12 13 21 22 TESTI B/V S/R F/D
VDD
B/V 13 S/R 21 F/D 22
A12329
-
AGCO 7
+ -
A12326 A12327 A12328
Continued on next page.
No. 6124-13/17
LC73815M
Continued from preceding page.
Pin No. Pin Internal connection
VDD OSCIN 15
15 16 OSCIN OSCOUT
VDD SOCOUT 16
A12330
VDD DATA 24
24 DATA
VDD
VDD
A12331
VDD ACK 25
25 29 ACK RES
RES 29
A12332
VDD DRCNT 30
30 DRCNT
A1233
EST/DR 26
26 27 31 34 EST/DR STD/DR TESTO1 TESTO2
STD/DR 27 TESTO1 31 TESTO2 34
VDD
VDD
A12334
No. 6124-14/17
LC73815M Pin Assignment
IN+ IN- GS AGND NC FSKOUT AGCO FSKIN NC AGND NC TESTI B/V NC OSCIN OSCOUT NC VSS
1 (I) 2 (I) 3 (O) 4 (O) 5 6 (O) 7 (O) 8 (I) 9
36 35 (O) 34 33 32 (O) 31 (I) 30 (I) 29 (O) 28
NC NC TESTO2 NC NC TESTO1 DRCNT RES RDO STD/DR EST/DR ACK DATA NC F/D S/R NC VDD
LC73815M
10 (I) 11 12 (I) 13 (I) 14 15 16 17 18 (O) 27 (O) 26 (I) 25 (I/O) 24 23 (I) 22 (I) 21 20 19
Top view
A12335
No. 6124-15/17
LC73815M Sample Application Circuit This example uses the DTMF receiver and the V.23 modulator, but does not use the FSK demodulator.
IN+ IN- GS AGNDO NC FSKOUT AGCO FSKIN NC AGNDI NC TESTI B/V NC OSCIN OSCOUT NC VSS
1 DTMF IN 0.1 F 3 100 k 4 33 k 5 FSK OUT 6 10 k 0.1 F 7 8 9 0.1 F 10 11 12 13 14 15 16 17 18 100 k 2
NC NC TESTO2 NC NC TESTO1 DRCNT RES RDO STD/DR EST/DR ACK DATA NC F/D S/R NC VDD
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 Power supply: 5 V FSK/DTMF switching Clock Data DTMF detection Reset (negative logic) CPU
0.1 F
10 F
Top view
A12336
No. 6124-16/17
LC73815M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of December, 2000. Specifications and information herein are subject to change without notice. PS No. 6124-17/17

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